Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, flash drives, digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
A typical flash memory device is a type of memory in which the array of memory cells is typically organized into memory blocks that can be erased and reprogrammed on block-by-block basis instead of one byte at a time. Changes in a threshold voltage of each of the memory cells, through erasing or programming of a charge storage structure (e.g., floating gate or charge trap) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. The data in a cell of this type is determined by the presence or absence of the charge in the charge storage structure.
The erase, programming, and read operations typically use some appropriate relatively high voltage that is applied to particular nodes of the memory cells. Due to physical constraints of the memory cell array architecture, a relatively large capacitance is typically charged to the high voltage in order to apply the voltage to the appropriate terminal for a particular period of time.
After a memory operation has been completed, there is typically time allotted for the operation to include discharging capacitance on the various high voltage nodes back to a lower voltage (e.g., 0V). However, when a sudden power down occurs while the memory device is performing an operation, the internal controller may not have the time to perform a suitable reset routine. The high voltage nodes can remain charged to the relatively high voltage for time periods longer than is desirable for the various memory operations. This can result in data corruption in both user data and configuration data since it might not be possible to exclude some accidental wrong path selection in the memory array while the device is powering down.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to discharge relatively high voltage nodes during a memory power down.